The converter described in that patent application is shown, by way of example, in accompanying FIG. 1. It essentially comprises, between a voltage source SE and a current source C, a succession of controllable switching cells CL1, CL2, . . . , CLn, each having two switches T1, T'1; T2, T'2; . . . ; Tn, T'n, with one pole of each of the two switches forming part of a pair of upstream poles and the other pole of each of the switches forming part of a pair of downstream poles, the pair of downstream poles of an upstream cell being connected to the pair of upstream poles of a downstream cell, and the pair of upstream poles of a first cell CL1 being connected to said current source C, while the pair of downstream poles of a last cell CLn is connected to said voltage source SE, the converter also comprising a respective capacitor C1, C2, . . . , Cn for each cell, except that the capacitor of the last cell may be omitted when said voltage source SE is suitable for performing the same role, each capacitor being connected between the two poles constituting the pair of downstream poles of its cell, the converter further having control means (not shown) governing the nominal operation of the converter and acting on the switches of the successive cells in such a manner that the two switches of any one cell are always in respective opposite conduction states (represented by control links such as lc1), such that in response to a cell control signal delivered by said control means, one of the two switches in a given cell is successively in a first conduction state and then in a second conduction state during a cyclically repeated converter chopper period, and such that in response to cell control signals that are identical but offset in time by a fraction of said converter chopper period, the switches of successive cells function respectively in the same manner but offset in time by said fraction of a period.
Preferably, said fraction of a period is equal to the reciprocal of the number n of cells, i.e. 2.pi./n, which is optimal with respect to harmonics generated on the output and which enables the voltages charged on the capacitors of the converter to be balanced naturally. Some other offset is nevertheless conceivable, as are different offsets between the various stages.
In such a converter, the successive capacitors C1, C2, . . . , Cn have respective increasing mean charge voltages, the mean charge voltage of the capacitor associated with each of said cells being equal to the product of a voltage VE delivered by said voltage source SE multiplied by the reciprocal of the number of cells in the converter and by the rank of the cell, i.e. VE/3, 2VE/3, VE when n=3, i.e. when the converter has only three cells.
Naturally, the above applies to other values of n, providing n is not less than two, and in particular when n is greater than three.
The term "multilevel converter" is used below to designate a converter that satisfies the above description.
An object of the present invention is to make provision in such a multilevel converter for the charge on each capacitor to remain in compliance with the above description, in spite of inevitable departures from nominal operating conditions.
To examine more easily how the charge ought nominally to vary on one of the capacitors of a multilevel converter as described above, reference is made to FIG. 2 which shows an arbitrary switching cell CLk together with its switches Tk and T'k, the capacitor Ck associated with the cell, and also the following cell CLk+1 and its switches Tk+1, T'k+1.
Given the coupling between the switches within each cell, Tk and T'k or Tk+1 and Tk+1, the set of two imbricated cells CLk and CLk+1 shown in FIG. 2 has four states:
a) a first state where Tk and Tk+1 are non-conducting, so the charge voltage on Ck does not change; PA1 b) a second state where Tk and Tk+1 are both conducting, so the charge voltage on Ck does not change either, since under those circumstances T'k and T'k+1 are non-conducting; PA1 c) a third state where Tk is conducting and Tk+1 is non-conducting, in which case the current source C forces a current Ik which is equal to I to flow through Tk while the current I'k through T'k is zero. It is the state of Tk+1 that forces the current Ik+1 to be zero, while the current I'k+1 is equal to I so the current I'ck through the capacitor Ck is equal to I; and PA1 d) a fourth state where Tk is non-conducting and Tk+1 is conducting, so the current source C forces a current I'k+1 equal to I through T'k while the current Ik through Tk is zero. The state of Tk+1 forces a current Ik+1 to be equal to I, while the current I'k+1 is zero, so the current Ick through the capacitor Ck is equal to I.
The currents I'ck=I'k+1 and Ick=Ik+1 deliver additional charge of opposite signs to the capacitor Ck in the above third and fourth states; the first situation is said to be negative and the second positive. The currents corresponding to these two states are forced by the current source. If the current source forces an exactly accurate DC, and everything else remains equal, then the currents forced by the current source during stages c) and d) are the same and in opposite directions at all times throughout the conduction periods of Tk and Tk+1 (which are nominally equal and offset in time, as mentioned above). This means that the charge on Ck is changed negatively and then positively by equal amounts, so it does not vary over one chopper period of the converter.
In an ideal system (accurate current source, infinite impedance), the currents Ick and I'ck are determined by the current source. In more practical terms, when the impedance of the current source is not infinite, the current through the current source depends on the voltage across its terminals and thus on the voltages Vck on the capacitors. For example, if it should happen that the charge voltage Vck is too high compared with its nominal value VE.k/n, for whatever reason, then there will result a discharging current I'ck tending to be greater and a charging current Ick tending to be smaller than they ought to be nominally, thereby tending to return the charge on the capacitor Ck to the value it ought to have. This explains that the operation of the multilevel converter is stable and can accommodate variations in amplitude, in either direction, both at the voltage source and at the current source. It is explained below that this nevertheless gives rise to problems in dynamic terms.
FIG. 3 is an example of operation of the multilevel converter of FIGS. 1 and 2 for a situation when n=3; pulse width modulation (PWM) type control is applied in order to deliver a sinusoidally modulated alternating voltage to the current source C, i.e., during successive periods p1, p2, p3, . . . in the operation of the converter (line t), the switches T1, T2, and T3 are successively conductive during time intervals that vary in accordance with a wave for modulating the output voltage, referred to below as the "modulating" wave. At each instant, the corresponding switches T'1, T'2, and T'3 are in the opposite positions.
Naturally, other modes of modulating the operation of the switches make it possible to obtain the same result, as is well known. Also clearly, the converter may also serve to deliver the current source C with any other waveform or with a regulated DC voltage.
Consideration is given initially to the period p1 in the operation of the converter. During this period, while any one of the switches T1, T2, and T3 is conducting, the other two are non-conducting. For each set of two cells and the capacitor between them, this corresponds to above-described states c) and d), in which the capacitor receives successive additional negative and positive charge, with the total value thereof being nominally zero. It should also be observed that while the imbricated cells CL1 and CL2 are in state d), adjacent cells CL2 and CL3 are in state c) such that capacitor C1 receives additional positive charge from the same current that provides additional negative charge to capacitor C2.
FIG. 3 also shows, by way of example, how the multilevel converter operates during periods p2, p3, etc . . . , during which the conduction periods of the switches T1, T2, and T3 become shorter, and then become longer until they exceed one-third of a period, in which case they overlap. Line VI shows the voltage that would ideally be transmitted to the current source, in particular if the capacitance of the capacitors was such that the additional charge in question did not significantly alter the voltage across their terminals. The voltage VI is expressed in fractions of the voltage VE from the voltage source SE, taking the negative pole of the voltage source SE as the voltage reference. It can then be seen that this voltage VI contains both a large fundamental at the frequency of the modulating wave, and also lower-amplitude harmonics at frequencies higher than the chopper frequency, or converter operating frequency, which are easily eliminated by a low-pass filter. Since the current is variable, integrating it by means of an arbitrary inductive element contained in the current source results in the converter supplying the current source with an AC of sinusoidal appearance having a period that is equal to the period of the fundamental of the output voltage.
Since the current varies sinusoidally, states c) and d) mentioned above will not convey equal additional amounts of charge to the capacitors of the converter, since between the above two states, the current will have had time to vary. Such variation is negligible only if the operating period of the switches is significantly greater than the frequency of the modulating wave.
It should also be expected that the AC supplied to the current source will not be exactly sinusoidal, but will be distorted in an asymmetrical manner. Likewise, errors in the levels of the control signals or in the signals they generate, or indeed differences in the switching times of the various switches involved, inevitably cause switch conduction durations to be unequal over an operating period of the converter, or will shift the conduction stages of the switches in time, or else will unbalance the currents charging and discharging the capacitors. Consequently, and in general, it is not possible in practice with a multilevel converter of the type described to guarantee that nominal operating conditions as described initially will, in fact be satisfied. Unfortunately, a persistent error in additional charge will lead to an error in one direction or the other in the charge on a capacitor, and thus to an error in its mean charge voltage, thereby giving rise to distortion at the operating frequency of the converter in the voltage delivered to the current source.
This effect is illustrated by trace VI' in FIG. 3 which is similar to the trace VI with the exception that capacitor C1 (FIG. 1) which is assumed to be charged to a voltage that is smaller than its nominal charge voltage prevents the converter from delivering pulses vi1, vi2, vi3 of constant amplitude, with the converter supplying instead, pulses such as vi1' that are of smaller amplitude (the scale is exaggerated to make it more readable) whenever the capacitor C1 is delivering its own charge voltage to the current source C, and pulses such as vi2' of greater amplitude whenever the capacitor C1 is subtracting its own voltage from the voltage delivered to the current source C, and finally also pulses such vi3' of unchanged amplitude whenever the capacitor C1 is not in the circuit. It is thus easy to see that this introduces into the signal VI' a disturbing component at said chopper frequency of the converter.
Such a disturbing component does not exist when the capacitors are charged to their respective nominal voltages. When such a component appears, it is generally harmful.
However, and above all, the voltages to which the switches are subjected are no longer substantially equal to the differences between the nominal charge voltages of two adjacent capacitors, i.e. the voltage of the voltage source divided by the number of stages in the converter. This can put the switches in danger.
Naturally, and as mentioned above, charge differences on the capacitors tend spontaneously to be reabsorbed, but that process takes time.
In addition, the spontaneous process is implemented via the current source. It is therefore slowed down whenever the current flowing through the current source is small.